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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD9801 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 world wide web site: http://www.analog.com fax: 617/326-8703 ? analog devices, inc., 1997 ccd signal processor for electronic cameras functional block diagram shp AD9801 pga pgacont1 pgacont2 clamp clpdm cds pblk pin din shd adcclk timing generator 23 29 30 19 21 22 16 27 26 37 48 47 18 cmlevel vrt vrb stby reference s/h 20 clpob clamp a/d 2 11 dout 33 acvdd 43 advdd 17 dvdd 12 drvdd 10 features 10-bit, 18 msps a/d converter 18 msps full-speed cds low noise, wideband pga internal voltage reference no missing codes guaranteed +3 v single supply operation low power cmos: 185 mw 48-pin tqfp package product description the AD9801 is a complete ccd signal processor developed for electronic cameras. it is well suited for both video conferencing and consumer level still camera applications. the signal processing chain is comprised of a high speed cds, variable gain pga and 10-bit adc. required clamping circuitry and an onboard voltage reference are also provided. the AD9801 operates from a single +3 v supply with a typical power consumption of 185 mw. the AD9801 is packaged in a space saving 48-pin thin-quad flatpack (tqfp) and is specified over an operating temperature range of 0 c to +70 c. product highlights 1. on-chip input clamp and cds clamp circuitry and high speed correlated double sampler allow for simple ac coupling to interface a ccd sensor at full 18 msps conversion rate. 2. on-chip pga the AD9801 includes a low noise, wideband amplifier with analog variable gain from 0 db to 31.5 db (linear in db). 3. 10-bit, high speed a/d converter a linear 10-bit adc is capable of digitizing ccd signals at the full 18 msps conversion rate. (typical dnl is 0.5 lsb and no missing code performance is guaranteed.) 4. low power at 185 mw, the AD9801 consumes a fraction of the power of presently available multichip solutions. the parts power- down mode (15 mw) further enhances its desirability in low power, battery operated applications. 5. digital i/o functionality the AD9801 offers three-state digital output control. 6. small package packaged in a 48-pin, surface-mount thin-quad flatpack, the AD9801 is well suited to very tight, low headroom designs.
C2C rev. 0 AD9801Cspecifications (t min to t max with acvdd = 3.15 v, advdd = 3.15 v, dvdd = 3.15 v, drvdd = 3.15 v unless otherwise noted) parameter min typ max units temperature range operating 0 70 c storage C65 150 c power supply voltage (for functional operation) acvdd 3.00 3.15 3.50 v advdd 3.00 3.15 3.50 v dvdd 3.00 3.15 3.50 v drvdd 3.00 3.15 3.50 v power supply current acvdd 39.5 ma advdd 14.6 ma dvdd 4.7 ma drvdd 0.07 ma power consumption normal operation 185 mw power-down mode 15 mw maximum shp, shd, adcclk rate 18 mhz adc resolution 10 bits differential nonlinearity 0.5 lsb no missing codes guaranteed adcclk rate 18 mhz reference top voltage 1.75 v reference bottom voltage 1.25 v input range 1.0 v p-p cds maximum input signal 500 mv p-p pixel rate 18 mhz pga 1 maximum gain 31.5 db high gain 15 19 23 db medium gain 0.5 3.5 6.5 db minimum gain C5 C1 +3 db clamp average black level (during clpob. only stable over pga range 0.3 v to 2.7 v) 32 lsb 1 pga test conditions: max gain pgacont1 = 2.7 v, pgacont2 = 1.5 v; high gain pgacont1 = 2.0 v, pgacont2 = 1.5 v; medium gain pgacont1 = 0.5 v, pgacont2 = 1.5 v; minimum gain pgacont1 = 0.3 v, pgacont2 = 1.5 v. specifications subject to change without notice. digital specifications parameter symbol min typ max units logic inputs high level input voltage v ih 2.4 v low level input voltage v il 0.6 v high level input current i ih 10 m a low level input current i il 10 m a input capacitance c in 10 pf logic outputs high level output voltage v oh 2.4 v low level output voltage v ol 0.6 v i oh 50 m a i ol 50 m a specifications subject to change without notice. (t min to t max with acvdd = 3.15 v, advdd = 3.15 v, dvdd = 3.15 v, drvdd = 3.15 v unless otherwise noted)
AD9801 C3C rev. 0 timing specifications parameter min typ max units adcclk clock period 55.6 ns adcclk high level period 24.8 27.8 ns adcclk low level period 24.8 27.8 ns shp, shd clock period 55.6 ns digital output delay 20 ns digital output data control mode1 mode2 digital output data (d9Cd0) 0 0 normal operation 0 1 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 1 1 high impedance (t min to t max with acvdd = 3.15 v, advdd = 3.15 v, dvdd = 3.15 v, drvdd = 3.15 v unless otherwise noted) absolute maximum ratings* parameter with respect to min max units advdd advss, subst C0.3 6.5 v acvdd acvss, subst C0.3 6.5 v dvdd dvss, dsubst C0.3 6.5 v drvdd drvss, dsubst C0.3 6.5 v shp, shd dsubst C0.3 dvdd + 2.0 v adcclk, clob, clpdm dsubst C0.3 dvdd + 0.3 v pgacont1, pgacont2 subst C0.3 acvdd + 0.3 v pin, din subst C0.3 acvdd + 0.3 v dout dsubst C0.3 drvdd + 0.3 v vrt, vrb subst C0.3 advdd + 0.3 v clamp_bias subst C0.3 acvdd + 0.3 v ccdbyp1, ccdbyp2 subst C0.3 acvdd + 0.3 v stby dsubst C0.3 dvdd + 0.3 v mode1, mode2 subst C0.3 advdd + 0.3 v drvss, dvss, acvss, advss subst, dsubst C0.3 +0.3 v junction temperature +150 c storage temperature C65 +150 c lead temperature (10 sec) +300 c * stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD9801 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. ordering guide model temperature package description package option* AD9801 0 c to +70 c 48-pin tqfp st-48 *st = thin quad flatpack package.
AD9801 C4C rev. 0 pin no. pin name type description 1 advss p analog ground 2C11 d0Cd9 do digital data outputs 12 drvdd p +3 v digital driver supply 13 drvss p digital driver ground 14 dsubst p digital substrate 15 dvss p digital ground 16 adcclk di adc sample clock input 17 dvdd p +3 v digital supply 18 stby di power down (active high) 19 pblk di pixel blanking (active low) 20 clpob di black level restore clamp (active low) 21 shp di reference sample clock input 22 shd di data sample clock input 23 clpdm di input clamp (active low) 24 dvss di digital ground 25 ccdbyp2 ao ccd bypass (decouple to analog ground through 0.1 m f) 26 din ai cds input (tie to pin 27 and ac-couple to ccd output through 0.1 m f) 27 pin ai cds input (see above) 28 ccdbyp1 ao ccd bypass (decouple to analog ground through 0.1 m f) 29 pgacont1 ai coarse pga gain control (0.3 vC2.7 v decoupled to analog ground through 0.1 m f) 30 pgacont2 ai fine pga gain control (0.3 vC2.7 v decoupled to analog ground through 0.1 m f) 31 acvss p analog ground 32 clamp_bias ao clamp bias level (decouple to analog ground through 0.1 m f) 33 acvdd p +3 v analog supply 34 acvdd ai +3 v analog supply 35 acvdd ai +3 v analog supply 36 int_bias1 ao internal bias level (decouple to analog ground through 0.1 m f) 37 cmlevel ao common-mode level (decouple to analog ground through 0.1 m f) 38 int_bias2 ao internal bias level (decouple to analog ground through 0.1 m f) 39 mode2 di adc test mode control (see digital output data control) 40 mode1 di adc test mode control (see digital output data control) 41 advss p analog ground 42 advdd p +3 v analog supply 43 advdd p +3 v analog supply 44 advss p analog ground 45 advss p analog ground 46 subst p substrate (connect to analog ground) 47 vrb ao bottom reference bypass (decouple to analog ground through 0.1 m f) 48 vrt ao top reference bypass (decouple to analog ground through 0.1 m f) pin configuration 24 23 22 21 20 19 18 17 16 15 14 13 37 38 39 40 41 42 43 44 45 46 47 48 1 2 3 4 5 6 7 8 9 101112 36 35 34 33 32 27 26 25 31 30 29 28 pin 1 identifier top view (not to scale) AD9801 vrt vrb subst advss advss advdd advdd advss mode1 mode2 int_bias2 cmlevel drvss dsubst dvss adcclk int_bias1 dvdd stby pblk clpob shp shd clpdm dvss acvdd acvdd acvdd clamp_bias acvss pgacont2 pgacont1 ccdbyp1 pin din ccdbyp2 advss (lsb) d0 d1 d2 d3 d4 d5 d6 d7 d8 (msb) d9 drvdd
AD9801 C5C rev. 0 equivalent input circuits dvdd drvdd dvss drvss figure 1. pins 2C11 (db0Cdb9) dvdd dsubst dvss 200 w figure 2. pin 21 (shp) and pin 22 (shd) dvdd dsubst dvss 200 w advdd advss 9.3k w figure 3. pin 16 (adcclk) figure 4. pin 37 (cmlevel) acvdd subst dvss 200 w figure 5. pin 25 (ccdbyp2) and pin 28 (ccdbyp1) acvdd subst acvss 50 w 10pf figure 6. pin 26 (din) and pin 27 (pin) acvdd subst acvdd 1k w 8k w 8k w 10k w pgacont1 pgacont2 figure 7. pin 29 (pgacont1) and pin 30 (pgacont2) acvss subst acvss 5.25k w 10k w 30k w 50 w figure 8. pin 32 (clamp bias) acvdd subst advss figure 9. pin 48 (vrt) and pin 47 (vrb)
AD9801 C6C rev. 0 effective pixel interval black level interval blanking interval dummy black interval effective pixel interval ccd shp shd clpob pblk clpdm adcclk adc data note: clpdm overwrites pblk clamp timing needs to be adjusted relative to ccd's black pixels figure 10. typical horizontal interval timing
AD9801 C7C rev. 0 ccd signal (delayed to match actual sampling edge) shd t id 35ns 35ns t od t h data n? data n n+1 n+2 n+3 n n+4 1234567 shp actual sampling edge adcclk digital out output load c l = 20pf output delay t od = 15ns latency = 5 cycles internal clock delay t hd = 3ns hold time t h = 2ns figure 11. timing diagram shp 15ns shd adcclk 5ns 10ns 5ns rising edge anywhere in this period ok inhibited period for adcclk to change pre-adc output latch pre-adc output latch data transition figure 12. adcclk timing edge
AD9801 C8C rev. 0 theory of operation introduction the AD9801 is a 10-bit analog-to-digital interface for ccd cameras. the block level diagram of the system is shown in figure 13. the device includes a correlated double sampler (cds), 0 dbC31 db variable gain amplifier (pga), black level correction loop, input clamp and voltage reference. the only external analog circuitry required at the system level is an emitter follower buffer between the ccd output and AD9801 inputs. clamp cds black level pga 10b adc ref out gain in figure 13. correlated double sampling (cds) cds is important in high performance ccd systems as a method for removing several types of noise. basically, two samples of the ccd output are taken: one with the signal present (data) and one without (reference). subtracting these two samples removes any noise that is commonor correlatedto both. figure 14 shows the block diagram of the AD9801s cds. the s/h blocks are directly driven by the input and the sampling function is performed passively, without the use of amplifiers. 10pf q1 s/h q2 s/h s out from ccd figure 14. this implementation relies on the off-chip emitter follower buffer to drive the two 10 pf sampling capacitors. only one capacitor at a time is seen at the input pin. the AD9801 actually uses two cds circuits in a ping pong fashion to allow the system more acquisition time. in this way, the output from one of the two cds blocks will be valid for an entire clock cycle. thus, the bandwidth requirement of the subsequent gain stage is reduced as compared to that for a single cds channel system. this lower bandwidth translates to lower power and noise. programmable gain amplifier (pga) the on-chip pga provides a (linear in db) gain range of 0 dbC31.5 db. a typical gain characteristic plot is shown in figure 15. only the range from 0.3 v to 2.7 v is intended for actual use. gain ?db pgacont1 ?volts 35 ?5 03 0.5 1 1.5 2 2.5 30 15 0 ? ?0 25 20 10 5 figure 15. as shown in figure 16, pga control is provided through the pgacont1 and pgacont2 inputs. pgacont1 provides coarse and pgacont2 fine (1/16) gain control. a pgacont1 pgacont2 pgacont1 = course control pgacont2 = fine control (1/16) figure 16. black level clamping for correct processing, the ccd signal must be referenced to a well established black level by the AD9801. at the edge of the ccd, there is a collection of pixels that are covered with metal to prevent any light penetration. as the ccd is read out, these black pixels provide a calibration signal that is used to establish the black level. the feedback loop shown in figure 17 is closed around the pga during the calibration interval (clpob = low) to set the black level. as the black pixels are being processed, an integrator block measures the difference between the input level and the desired reference level. this difference, or error, signal is amplified and passed to the cds block where it is added to the incoming pixel data. as a result of this process, the black pixels are digitized at one end of the adc range, taking maximum advantage of the available linear range of the system. pga adc in clpob neg ref integrator cds figure 17.
AD9801 C9C rev. 0 the actual implementation of this loop is slightly more compli- cated as shown in figure 18. because there are two separate cds blocks, two black level feedback loops are required and two offset voltages are developed. figure 18 also shows an additional pga block in the feedback loop labeled rpga. pga adc in clpob neg ref control cds1 rpga2 int2 cds1 rpga1 int1 figure 18. the rpga uses the same control inputs as the pga, but has the inverse gain. the rpga functions to attenuate by the same factor as the pga amplifies, keeping the gain and bandwidth of the loop constant. input bias level clamping the buffered ccd output is connected to the AD9801 through an external coupling capacitor. the dc bias point for this coupling capacitor is established during the clamping (clpdm = low) period using the dummy clamp loop shown in figure 19. when closed around the cds, this loop establishes the desired dc bias point on the coupling capacitor. black level clp ccd input clamp cds clpdm to adc pga figure 19. input blanking in some applications, the AD9801s input may be exposed to large signals from the ccd. these signals can be very large, relative to the AD9801s input range, and could thus saturate on-chip circuit blocks. recovery time from such saturation conditions could be substantial. to avoid problems associated with processing these transients, the AD9801 includes an input blanking function. when active (pblk = low), this function stops the cds operation and allows the user to disconnect the cds inputs from the ccd buffer. if the input voltage exceeds the supply rail by more than 0.3 v, protection diodes will be turned on, increasing current flow into the AD9801 (see equivalent input circuits). such voltage levels should be externally clamped to prevent device damage or reliability degradation. 10-bit analog-to-digital converter (adc) the adc employs a multibit pipelined architecture, which is well-suited for high throughput rates while being both area and power efficient. the multistep pipeline presents a low input capacitance resulting in lower on-chip drive requirements. a fully differential implementation was used to overcome head- room constraints of the single +3 v power supply. differential reference the AD9801 includes a 0.5 v reference based on a differential, continuous-time bandgap cell. use of an external bypass capacitor reduces the reference drive requirements, thus lowering the power dissipation. the differential architecture was chosen for its ability to reject supply and substrate noise. recommended decoupling shown in figure 20. vrt ref vrb 1? 0.1? 0.1? figure 20. internal timing the AD9801s on-chip timing circuitry generates all clocks necessary for operation of the cds and adc blocks. the user needs only to synchronize the shp and shd clocks with the ccd waveform, as all other timing is handled internally. the adcclk signal is used to strobe the output data, and can be adjusted to accommodate desired timing.
AD9801 C10C rev. 0 application information generating clock signals for best performance, the AD9801 should be driven by 3 v logic levels. as shown in the equivalent input circuits, the use of 5 v logic for adcclk will turn on the protection diode to dvdd, increasing the current flow into this pin. as a result, noise and power dissipation will increase. the cds clock inputs, shp and shd, have additional protection and can withstand direct 5 v levels. external clamping diodes or resistor dividers can be used to translate 5 v levels to 3 v levels, but the lowest power dissipa- tion is achieved with a logic transceiver chip. national semi- conductors 74lvx4245 provides a 5 v to 3 v level shift for up to eight clock signals, and features a three-state option and low power consumption. philips semiconductor and quality also manufacture similar devices. digitally programmable gain control the AD9801s pga is controlled by an analog input voltage of 0.3 v to 2.7 v. in some applications, digital gain control is preferable. figure 21 shows a circuit using analog devices ad8402 digital potentiometer to generate the pga control voltage. the ad8402 functions as two individual potentiom- eters, with a serial digital interface to program the position of each wiper over 256 positions. the device will operate with 3 v or 5 v supplies, and features a power-down mode and a reset function. to keep external components to a minimum, the ends of the potentiometers can be tied to ground and +3 v. one pot is used for the coarse gain adjust, pgacont1, with steps of about 0.2 db/lsb. the other pot is used for fine gain control, pgac ont2, and is capable of around 0.01 db steps if all eight bits are used. the two outputs should be filtered with 1 m f or larger capacitors to minimize noise into the pgacont pins of the AD9801. the disadvantage of this circuit is that the control voltage will be supply dependent. if additional precision is required, an external op amp can be used to amplify the vreft (1.75 v) or vrefb (1.25 v) pins on the AD9801 to the desired voltage level. these reference voltages are stable over the operating supply range of the AD9801. low power, low cost, rail-to-rail output amplifiers such as the ad820, op150 and op196 are specified for 3 v operation. alternatively, a precision voltage 1 2 3 4 7 6 5 ad8402-10 14 13 12 11 10 9 8 +3v +3v cs sdi clk shdn rs 1? pgacont2 1? 0.1? +3v pgacont1 figure 21. digital control of pga reference may be used. the ref193 from analog devices features low power, low dropout performance, maintaining a 3 v output with a minimum 3.1 v supply when lightly loaded. power and grounding recommendations the AD9801 should be treated as an analog component when used in a system. the same power supply and ground plane should be used for all of the pins. in a two-ground system, this requires that the digital supply pins be decoupled to the analog ground plane and the digital ground pins be connected to analog ground for best noise performance. if any pins on the AD9801 are connected to the system digital ground, noise can capacitively couple inside the AD9801 (through package and die parasitics) from the digital circuitry to the analog circuitry. separate digital supplies can be used, particularly if slightly different driver supplies are needed, but the digital power pins should still be decoupled to the same point as the digital ground pins (analog ground plane). if the AD9801 digital outputs need to drive a bus or substantial load, a buffer should be used at the AD9801s outputs, with the buffer referenced to system digital ground. in some cases, when system digital noise is not substantial, it is acceptable to split the ground pins on the AD9801 to separate analog and digital ground planes. if this is done, be sure to connect the ground pins together at the AD9801. to further improve performance, isolating the driver supply drvdd from dvdd with a ferrite bead can help reduce kickback effects during major code transitions. alternatively, the use of damping resistors on the digital outputs will reduce the output risetimes, reducing the kickback effect.
AD9801 C11C rev. 0 avss 6 7 4 3 2 u6 ad707 c50 0.1? c55 0.01? c56 0.1? c49 0.01? r14 68 w c37 0.1? avcc cw r6 10k w tp25 c70 10? 16v pgacont1 avcc 24 23 22 21 20 19 18 17 16 15 14 13 36 35 34 33 32 27 26 25 31 30 29 28 37 38 39 40 41 42 43 44 45 46 47 48 123456789101112 u1 AD9801 advss drvdd d0 (lsb) d1 d2 d3 d4 d5 d6 d7 d8 d9 (msb) drvss dvss clpdm shd shp clpob pblk stby dvdd adcclk dvss dsubst vrt vrb subst advss advdd advdd advss clamp_bias mode1 mode2 int_bias2 cmlevel advss acvdd acvdd acvdd acvss pgacont2 pgacont1 ccdbyp1 pin din ccdbyp2 c14 0.1? c28 0.01? vdd d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 c5 0.1? c6 0.1? c2 0.1? c1 1? c3 0.1? c4 0.1? vdd c8 0.1? c23 0.1? pin c10 2? c9 2? c12 0.1? c7 0.1? c61 0.1? pgacont1 pgacont2 vdd tp5 pblk clpob stby shp shd clpdm adcclk c13 0.1? c29 0.01? vdd din 0.1? vdd cw 1k w jp3 jp2 jp1 jp4 fb4 c11 0.1? c46 0.1? c47 22? fb1 tp28 c66 0.1? vdd +3v jp1 c45 0.1? c44 22? fb2 tp27 c67 0.1? +5v jp2 avcc int_bias1 c40 0.1? c41 22? fb3 tp26 c68 0.1? avss ?v jp3 tp29 gnd jp5 avcc avss 6 7 4 3 2 u7 ad707 c51 0.1? c57 0.01? c52 0.1? c54 0.01? r15 68 w c36 0.1? avcc cw r7 10k w tp24 c71 10? 16v pgacont2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 40 pin header d9 (msb) d8 d7 d6 d5 d4 d3 d2 d1 d0 (lsb) adcclk figure 22. AD9801eb schematic evaluation board figure 22 shows the schematic for the AD9801 evaluation board. notice the use of a common ground and supply for the AD9801, and the extensive supply and reference decoupling.
AD9801 C12C rev. 0 outline dimensions dimensions shown in inches and (mm). c2975C12C1/97 printed in u.s.a. 48-terminal plastic thin quad flatpack (st-48) 0.354 (9.00) bsc 0.276 (7.0) bsc 1 12 13 25 24 36 37 48 top view (pins down) 0.276 (7.0) bsc 0.354 (9.00) bsc 0.011 (0.27) 0.006 (0.17) 0.019 (0.5) bsc seating plane 0.063 (1.60) max 0 min 0 ?7 0.006 (0.15) 0.002 (0.05) 0.030 (0.75) 0.018 (0.45) 0.057 (1.45) 0.053 (1.35) 0.030 (0.75) 0.018 (0.45) 0.007 (0.18) 0.004 (0.09)

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